The present invention is related to an image processing apparatus in which, for instance, data produced by sampling a supplied picture signal is written into a memory, and then read timing of this stored data is adjusted.
Normally, a total number of pixels per 1 line of a picture signal is determined. For instance, in the case of the NTSC (National Television System Committee) technical specification, assuming now that a sampling frequency of a horizontal direction is selected to be 13.5 MHz, a total number of pixels per 1 line becomes 858 pixels. However, in a so-called “non-standard signal”, these 858 pixels are not always employed. Also, even when a standard signal is used, in such a case that an asynchronous sampling clock is used in a digital sampling process operation, sampling positions are made different from each other by using this asynchronous sampling clock. As a result, pixel numbers may be made different from each other.
In an actual case, when a total pixel number of a 1H line is not constant, such a phenomenon happens to occur in an image displayed on a monitor, resulting in a derioration of an image (picture) quality. As this phenomenon, zigzag portions are produced in edges within the image, and/or a longitudinal straight line within the image is shifted. As a method of maintaining image qualities, a pixel adjusting circuit employs a FIFO (First-In First-Out) memory, a 1-H judging unit, a write control unit, and a read control unit. The FIFO memory stores thereinto data to be inputted, and outputs such a data that has been stored by performing a time adjustment. Although a memory capacity of the FIFO memory is not limited, 0.5 to 1 k words are properly selected as this memory capacity. Generally speaking, in order that a memory capacity of a FIFO memory is saved and a data transfer operation is carried out in a higher efficiency, this memory capacity is selected to be smaller than a 1H line.
The 1-H judging unit contains a counter and a pixel number judging unit. While an interval from a threshold which has been previously set with respect to the horizontal sync signal up to a next threshold is defined as an interval of a 1H line, the counter counts this interval by using a sampling clock, and then sets the count value as a total pixel number within the 1H line in an input picture signal. The counter supplies the count value to the pixel number judging unit. In this case, a horizontal sync signal corresponds to such a signal that is obtained by sync-separating the supplied picture signal by the existing sync separating circuit. The horizontal sync signal is employed as a signal for resetting the counter every 1H line.
While the pixel number judging unit employs the supplied count value as the pixel number and compares this count value with a predetermined pixel number (standard value) which is written into the memory within the 1H line, this pixel number judging unit sends data to the write control unit, and this data is controlled in response to a position of data to be written. This data is a comparison result, and when a count value within a 1H line is smaller than the predetermined pixel value, the pixel numbers judging unit outputs (−), whereas when a count value within the 1H line is equal to the predetermined pixel value, the pixel number judging unit outputs (0). Then when a count value within a 1H line is larger than the predetermined pixel value, the pixel number judging unit outputs (+). Also, the pixel number judging unit also supplies a difference between a count value and a predetermined pixel number.
Although not shown in the drawing, the write control unit contains a write control circuit and a write counter. The write control unit owns such a function capable of controlling a write address of input data that is supplied to the FIFO memory. To accomplish this function, the write control circuit outputs a control signal for designating starting of a counting operation to the write counter, and sets an interval between a write starting address and a read starting address in the FIFO memory as a phase difference. In the case that the storage capacity of the FIFO memory is assumed as “n”, this phase difference is set to a half value of this capacity “n”. The write control circuit supplies this half capacity value (n/2) to the read control circuit. Also, the write control circuit also performs a write prohibit control operation with respect to the write counter. The write counter counts input data in response to a sampling clock that is supplied from the commencement of the counting operation, and outputs the count value as a write address to the FIFO memory. This count value is also supplied to the read control circuit.
Also, the read control unit contains both a read control circuit and a read counter. The read control unit owns such a function that a commencement of the reading operation is notified to the read counter, and a control signal for starting the counting operation is outputted. The read counter starts its counting operation in response to the supplied control signal, and subsequently is operated in a free running mode in response to the sampling clock. The read counter supplies the count value as a read address to the FIFO memory.
Operations executed in the pixel adjusting circuit will now be simply explained. The sampled input data are sequentially written into the FIFO memory from a head of the 1H line, and after predetermined time has passed, the data written in this FIFO memory are read. In this case, the memory capacity of the FIFO memory is equal to “n”, and corresponds to such a memory capacity smaller than the predetermined sampling number (pixels) within the 1H line.
In this case, the predetermined time corresponds to the above-described phase difference. After a half of the phase difference has been written into the FIFO memory, the reading operation is commenced. A position of the phase difference is n/2. Also, a pixel number obtained in the case that a 1H line is sampled based upon the above-described sampling frequency of 13.5 MHz is equal to 858.
The pixel number judging unit notifies to the write control unit, a first case that the pixel number of the 1H line is equal to the standard value (858); a second case that the pixel number of the 1H line is larger than the standard value (858); and also, a third case that the pixel number of the 1H line is smaller than the standard value (858). In the first case, the write control unit judges that this condition is the normal operation, and thus, supplies the write address to the FIFO memory. While the relationship of the phase difference is maintained, the read control unit supplies the read address to the FIFO memory. As a result, the input data are sequentially and continuously inputted/outputted.
However, in the second case in which the count value in the pixel number judging unit is different from the standard value, the write control circuit performs such a write prohibit control operation. That is, both such a judgment result (+) that the pixel number of the input data is larger than the standard value per 1H line, and a difference of the supplied pixel number are not written into the FIFO memory. In other words, the increased pixels within the supplied input data are not written into the FIFO memory. Since this write prohibit control operation is carried out, the same pixel number as the standard value is written into the FIFO memory as the pixel number of the line, so that the read circuit reads out the data under the same control as the normal control operation.
To the contrary, in the third case, the write control circuit executes such a write controlling operation. That is, this write control circuit writes the input data of the 1H line, skips addresses of shortages of pixel values, and then executes the process operation with respect to the next 1H line. Also, in this third case, the read control unit executes the same control operation as the normal operation and outputs a predetermined pixel number.
As explained above, when the write control unit executes the write control operation of the input data with respect to the FIFO memory, this write control units manages the phase difference so as to perform the pixel management. Also, in this process operation, either a shift of the phase differences or a difference thereof is given to both an input signal and an output signal. This difference is absorbed by executing such a process operation that the phase difference is returned to a default value every 1 field, and thus, this difference may be canceled. Since such a process operation is carried out so as to adjust the pixel number per 1H line, the picture output may be properly obtained.
On the other hand, in the third case, the write address is adjusted in order to control that the shortage of addresses are skipped on the data writing side, whereas the normal read control is carried out so as to output a constant pixel number in the normal manner. In this case, the input data that has been written in the memory area before this shortage of these pixel numbers occurred is not rewritten, but is left. This memory area corresponds to the addresses skipped by the write control operation of the FIFO memory. As a consequence, if the data reading operation is carried out in the normal manner, then this remaining data is also read. In the case that there is a difference between the present data and the data that has been written before the shortage of pixel numbers occurred, or there is no correlative relationship between these data, dot noise will appear as so-called “flickering noise” on the display screen in correspondence with this pixel.
Also, since the input error is processed by the error absorbing process operation for resetting the input data in a batch manner every 1 field, either the shift or the difference is gradually stored during 1 field, and therefore is gradually increased. As a result, such a phenomenon will occur in the resulting image. That is, such an observation is made that an upper portion of this image is shifted from a lower portion thereof, and disturbance produced in a half way of the image is continued until the end of this field.